Some simulators already
support a set of SystemVerilog string method extensions that handle regular
expressions such as str.match() and str.search().
For example,
string str =
"Thirumoorthy";
result = str.match(“Thiru.*”); // returns true ( i.e if the pattern is matched with the str).
If you are using the
UVM, there is a DPI routine that does the same thing
result = uvm_pkg::uvm_re_match(“pattern”,str); //returns 0 if matches
With uvm_re_match,
sometimes regular expressions might have problem if you are not careful with
the expression.
For example,
result = uvm_pkg::uvm_re_match(“Thiru.*”,str); //returns 1 which is a mismatch
here . is matched as dot instead of wildcard
whereas
result = uvm_pkg::uvm_re_match(“Thiru*”,str); //returns 0 which is a match
But SV regular
expression works consistently.
