We as verification engineers have a laborious task to do when compared to designers. So what we can we tell to designers/architects to make design as verification friendly?
1. Add embedded assertions within RTL
2. Add interrupts and log registers for error scenarios.
3. If there are any big counters or timers, we can ask them to add a bit to count in chunks like 128 or 256 or 1K etc.
4. Add registers to capture some of the status between the modules. This will be useful in post-silicon as well.
5. Optimize the design for features and eliminate unnecessary logic. Any additional logic adds costs verification efforts.
6. Add statistical counters for crucial data path
7. Add display statements for printing the packets going thru different modules before coming out. This will be very useful for debugging.
1. Add embedded assertions within RTL
2. Add interrupts and log registers for error scenarios.
3. If there are any big counters or timers, we can ask them to add a bit to count in chunks like 128 or 256 or 1K etc.
4. Add registers to capture some of the status between the modules. This will be useful in post-silicon as well.
5. Optimize the design for features and eliminate unnecessary logic. Any additional logic adds costs verification efforts.
6. Add statistical counters for crucial data path
7. Add display statements for printing the packets going thru different modules before coming out. This will be very useful for debugging.
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