Suppose if we are assigned a new block which has the simulation running for long time and we have to reduce the sim time. What are the techniques that we can use ?
1. Reduce the number of packets or queues etc.
2. Do the backdoor loading of registers or memories.
3. Reduce the verbosity and run without dump
4. In case of full chip, disable the blocks which are not used
5. Do profiling and see where the maximum time/memory spent. Since complexity of benches are going high, randomization could be time consuming with lot of constraints and move some of them to post_randomize. Also if lot of memories are used in the benches, we have to make sure by way of memory manager to have optimum allocation and avoid memory explosion.
6. Reduce the number of objections raised/dropped if any.
7. Check the SV concurrent assertions which could be time consuming.
8. Simulation with Serdes/PHY takes time. We can try running without it.
9. Run the simulation with bigger and faster machines
10. Try using right switches with simulator. For example,
+nospecify : Suppresses module path delays and timing checks in specify blocks. This option can significantly improve simulation performance. This can be most effective at functional gate level simulations.
+notimingchecks : Tells VCS to ignore timing check system tasks when it compiles your design. Note that +nospecify is a superset of +notimingchecks. Avoid any debug switches like +cli, +acc, -line etc. They can significantly slow down simulations.
1. Reduce the number of packets or queues etc.
2. Do the backdoor loading of registers or memories.
3. Reduce the verbosity and run without dump
4. In case of full chip, disable the blocks which are not used
5. Do profiling and see where the maximum time/memory spent. Since complexity of benches are going high, randomization could be time consuming with lot of constraints and move some of them to post_randomize. Also if lot of memories are used in the benches, we have to make sure by way of memory manager to have optimum allocation and avoid memory explosion.
6. Reduce the number of objections raised/dropped if any.
7. Check the SV concurrent assertions which could be time consuming.
8. Simulation with Serdes/PHY takes time. We can try running without it.
9. Run the simulation with bigger and faster machines
10. Try using right switches with simulator. For example,
+nospecify : Suppresses module path delays and timing checks in specify blocks. This option can significantly improve simulation performance. This can be most effective at functional gate level simulations.
+notimingchecks : Tells VCS to ignore timing check system tasks when it compiles your design. Note that +nospecify is a superset of +notimingchecks. Avoid any debug switches like +cli, +acc, -line etc. They can significantly slow down simulations.
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